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ltp5901-ipr/ltp5902-ipr 1 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr typical application network features description smartmesh ip network manager 2.4ghz 802.15.4e wireless embedded manager l tp5901 / 2- ipr features n complete radio transceiver, embedded processor , and networking software for forming a self-healing mesh network n smartmesh ? networks incorporate: n time synchronized network-wide scheduling n per transmission frequency hopping n redundant spatially diverse topologies n network-wide reliability and power optimization n nist certified security n smartmesh networks deliver: n >99.999% network reliability achieved in the most challenging rf environments n sub 50a routing nodes n compliant to 6lowpan internet protocol (ip) and ieee 802.15.4e standards n manages networks of up to 100 nodes n sub 1ma average current consumption enables battery powered network management n rf modular certification include usa, canada, eu, japan, taiwan, korea, india, australia and new zealand n pcb assembly with chip antenna ( lt p 5901-ipr) or with mmcx antenna connector ( lt p 5902-ipr) smartmesh ip ? wireless sensor networks are self man - aging, low power internet protocol (ip) networks built from wireless nodes called motes. the lt p ?5901-ipr/ ltp5902-ipr is the ip manager product in the eterna ? * family of ieee 802.15.4e printed circuit board assembly solutions, featuring a highly integrated, low power radio design by dust networks ? as well as an arm cortex- m3 32- bit microprocessor running dust s embedded smart - mesh ip networking software.based on the ietf 6lowp an and ieee-802.15.4e stan - dards, the l tp5901/2- ipr runs smartmesh ip network management software to monitor and manage network per formance and provide a data ingress/egress point via a uar t interface. the smartmesh ip software provided with the l tp5901/2- ipr is fully tested and validated, and is readily configured via a software application program - ming interface. with dust s time-synchronized smartmesh ip networks, all motes in the network may route, source or terminate data, while providing many years of battery powered operation. smartmesh ip motes deliver a highly flexible network with proven reliability and low power performance in an easy-to-integrate platform. l , lt, ltc, ltm, linear technology, dust, dust networks, eterna, smartmesh and the linear logo are registered trademarks and ltp, smartmesh ip and the dust networks logo are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7375594, 7420980, 7529217, 7791419, 7881239, 7898322, 8222965. * eterna is dust networks low power radio soc architecture. 59012ipr ta01 controller sensor in + in C spi lt c ? 2379-18 ltp5901/2-ipm uart uart mote expanded view antenna ltp5901-ipr host application downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 2 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr table of contents network features .......................................... 1 ltp5901/2-ipr features .................................. 1 typical application ........................................ 1 description.................................................. 1 smartmesh network overview ........................... 3 absolute maximum ratings .............................. 4 pin configuration .......................................... 4 order information .......................................... 5 recommended operating conditions ................... 5 dc characteristics ......................................... 5 radio specifications ...................................... 6 radio receiver characteristics .......................... 6 radio transmitter characteristics ....................... 7 digital i/o characteristics ................................ 7 temperature sensor characteristics .................... 7 system characteristics ................................... 8 uart ac characteristics .................................. 8 time ac characteristics .................................. 9 radio_inhibit ac characteristics ..................... 10 flash ac characteristics ................................. 10 flash spi slave ac characteristics .................... 10 external bus ac characteristics ........................ 11 typical performance characteristics .................. 14 pin functions .............................................. 19 operation................................................... 22 power supply .......................................................... 23 supply monitoring and reset ................................. 23 precision timing ..................................................... 23 application time synchronization .......................... 23 time references ..................................................... 23 radio ...................................................................... 24 uarts ..................................................................... 24 api uart protocol ................................................. 24 cli uart ................................................................ 25 autonomous mac ................................................... 25 security .................................................................. 25 temperature sensor ............................................... 25 radio inhibit ........................................................... 25 software installation ............................................... 26 flash data retention ............................................... 26 networking ............................................................. 26 applications information ................................ 29 regulatory and standards compliance ................... 29 soldering information ............................................. 29 related documentation .................................. 30 package description ..................................... 31 revision history .......................................... 33 typical application ....................................... 34 related parts .............................................. 34 downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 3 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr smartmesh network overview a smartmesh network consists of a self-forming multi-hop, mesh of nodes, known as motes, which collect and relay data, and a network manager that monitors and manages network performance and security, and exchanges data with a host application. smartmesh networks communicate using a time slotted channel hopping? (tsch) link layer, pioneered by dust networks. in a tsch network, all motes in the network are synchronized to within less than a millisecond. time in the network is organized into timeslots, which enables collision-free packet exchange and per-transmission channel-hopping. in a smartmesh network, every device has one or more parents (e.g. mote 3 has motes 1 and 2 as parents) that provide redundant paths to overcome communications interruption due to interference, physical obstruction or multi-path fading. if a packet transmission fails on one path, the next retransmission may try on a different path and different rf channel. a network begins to form when the network manager instructs its onboard access point (ap) radio to begin send - ing?advertisements packets that contain information that enables a device to synchronize to the network and request to join. this message exchange is part of the?security?hand - shake that establishes encrypted communications between the manager or application, and mote. ?once motes have joined the network, they maintain synchronization through time corrections when a packet is acknowledged. to the network manager in packets called health reports. the network manager uses health reports to continually optimize the network to maintain > 99.999% data reliability even in the most challenging rf environments. the use of tsch allows smartmesh devices to sleep in- between scheduled communications and draw very little power in this state. motes are only active in timeslots where they are scheduled to transmit or receive, typically resulting in a duty cycle of < 1%. the optimization soft - ware in the network manager coordinates this schedule automatically. when combined with the eterna low power radio, every mote in a smartmesh network even busy routing ones can run on batteries for years. by default, all motes in a network are capable of routing traffic from other motes, which simplifies installation by avoiding the complexity of having distinct routers vs non-routing end nodes. motes may be configured as non-routing to further reduce that particular mote s power consumption and to support a wide variety of network topologies. an ongoing discovery process ensures that the network continually discovers new paths as the rf conditions change. in addition, each mote in the network tracks per - formance statistics (e.g. quality of used paths, and lists of potential paths) and periodically sends that information at the heart of smartmesh motes and network managers is the eterna ieee 802.15.4e system-on-chip (soc), fea - turing dust networks highly integrated, low power radio design, plus an arm cortex- m3 32- bit microprocessor running smartmesh networking software. the smartmesh networking software comes fully compiled yet is configu - rable via a rich set of application programming interfaces (apis) which allows a host application to interact with the network, e.g. to transfer information to a device, to configure data publishing rates on one or more motes, or to monitor network state or performance metrics. data publishing can be uniform or different for each device, with motes being able to publish infrequently or faster than once per second as needed. host application ap network manager 59012ipr sno01 mote 2 mote 1 mote 3 all nodes are routers. they can transmit and receive. this new node can join anywhere because all nodes can route. 59012ipr sno02 downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 4 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr pin configuration absolute maximum ratings supply voltage on vsupply .................................. 4.20v input voltage on ai_0/1/2/3 inputs ........................ 1.98v voltage on any digital i/o pin .... C 0.3v to vsupply + 0.3v input rf level ...................................................... 10dbm storage temperature range (note 3) ..... C 55 c to 105 c (notes 1, 2) operating temperature range l tp5901 i/lpt5902i ............................. C 40 c to 85 c caution : this part is sensitive to electrostatic discharge (esd). it is very important that proper esd precautions be observed when handling the l tp5901 /l tp5902 -ipr. pin functions shown in italics are currently not supported in software. 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 6665 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 gnd reserved nc reservedreserved reserved reserved reserved reserved reserved gnd reserved ncnc resetn tdi tdo tms tck gnd reserved reserved reserved reserved eb_data_7 eb_data_6 eb_data_4 eb_data_0 nc gnd gndnc radio_inhibit timen uart_tx uart_tx_ctsn uart_tx_rtsn uart_rx uart_rx_ctsn uart_rx_rtsn gnd vsupply reserved nc nc flash_p_enn / eb_io_le1 eb_io_oen eb_io_wen reserved / uartc1_rx reserved / uartc1_tx eb_io_cs0n eb_data_5 eb_data_2 eb_data_3 gnd eb_addr_0 eb_addr_1 ipcs_ssn eb_io_le2 gnd ipcs_miso uartco_rx / eb_data_1 uartco_tx / eb_io_le0 pc package 66-lead pcb ipcs_sck ipcs_mosi gnd 31 32 33 34 35 36 downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 5 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr order information lead free finish ? part marking* package description temperature range ltp5901ipc-ipma#pbf ltp5901ipc-ipma#pbf 66-lead (42mm 24mm 5.5mm) pcb with chip antenna C40c to 85c ltp5902ipc-ipma#pbf ltp5902ipc-ipma#pbf 66-lead (37.5mm 24mm 5.5mm) pcb with mmcx connector C40c to 85c ?this product ships with the flash erased at the time of order. oems will need to program devices during development and manufacturing. for legacy part numbers and ordering information go to: www.linear.com/ltp5901-ipr#orderinfo or www.linear.com/ltp5902-ipr#orderinfo for more information on lead free part marking, go to: http://www.linear.com/leadfree/ *the temperature grade is identified by a label on the shipping container. recommended operating conditions symbol parameter conditions min typ max units vsupply supply voltage including noise and load regulation l 2.1 3.76 v supply noise 50hz to 2mhz l 250 mv operating relative humidity non-condensing l 10 90 % rh temperature ramp rate while operating in network l C8 8 c/min the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. dc characteristics operation/state conditions min typ max units power-on reset during power-on reset, maximum 750s + vsupply rise time from 1v to 1.9v 12 ma doze ram on, arm cortex-m3, flash, radio, and peripherals off, all data and state retained, 32.768khz reference active 1.2 a deep sleep ram on, arm cortex-m3, flash, radio, and peripherals off, all data and state retained, 32.768khz reference inactive 0.8 a in-circuit programming resetn and flash_p_enn asserted, ipcs_sck at 8mhz 20 ma peak operating current 8dbm 0dbm system operating at 14.7mhz, radio transmitting, during flash write. maximum duration 4.33 ms. 30 26 ma ma active arm cortex-m3, ram and flash operating, radio and all other peripherals off. clock frequency of cpu and peripherals set to 7.3728mhz, vcore = 1.2v 1.3 ma flash write single bank flash write 3.7 ma flash erase single bank page or mass erase 2.5 ma radio tx 0dbm 8dbm current with autonomous mac managing radio operation, cpu inactive. clock frequency of cpu and peripherals set to 7.3728mhz. 5.4 9.7 ma ma radio rx current with autonomous mac managing radio operation, cpu inactive. clock frequency of cpu and peripherals set to 7.3728mhz. 4.5 ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 6 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr parameter conditions min typ max units frequency band l 2.4000 2.4835 ghz number of channels l 15 channel separation l 5 mhz channel center frequency where k = 11 to 25, as defined by ieee.802.15.4 l 2405 + 5 ? (k-11) mhz raw data rate l 250 kbps antenna pin esd protection hbm per jedec jesd22-a114f (note 2) 6000 v range indoor outdoor free space 25c, 50% rh, +2dbi omni-directional antenna, antenna 2m above ground 100 300 1200 m m m radio specifications the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. parameter conditions min typ max units receiver sensitivity packet error rate (per) = 1% (note 5) C93 dbm receiver sensitivity per = 50% C95 dbm saturation maximum input level the receiver will properly receive packets 0 dbm adjacent channel rejection (high side) desired signal at C82dbm, adjacent modulated channel 5mhz above the desired signal, per = 1% (note 5) 22 dbc adjacent channel rejection (low side) desired signal at C82dbm, adjacent modulated channel 5mhz below the desired signal, per = 1% (note 5) 19 dbc alternate channel rejection (high side) desired signal at C82dbm, alternate modulated channel 10mhz above the desired signal, per = 1% (note 5) 40 dbc alternate channel rejection (low side) desired signal at C82dbm, alternate modulated channel 10mhz below the desired signal, per = 1% (note 5) 36 dbc second alternate channel rejection desired signal at C82dbm, second alternate modulated channel either 15mhz above or below , per = 1% (note 5) 42 dbc co-channel rejection desired signal at C82dbm, undesired signal is an 802.15.4 modulated signal at the same frequency, per = 1% C6 dbc lo feed through C55 dbm frequency error tolerance (note 6) 50 ppm symbol error tolerance 50 ppm received signal strength indicator (rssi) input range C90 to -10 dbm rssi accuracy 6 db rssi resolution 1 db radio receiver characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 7 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr parameter conditions min typ max units output power high calibrated setting low calibrated setting delivered to a 50 load 8 0 dbm dbm spurious emissions 30mhz to 1000mhz 1ghz to 12.75ghz 2.4ghz ism upper band edge (peak) 2.4ghz ism upper band edge (average) 2.4ghz ism lower band edge conducted measurement with a 50 single-ended load, 8dbm output power. all measurements made with max hold. r bw = 120khz, v bw = 100hz r bw = 1mhz, v bw = 3mhz r bw = 1mhz, v bw = 3mhz r bw = 1mhz, v bw = 10hz r bw = 100khz, v bw = 100khz < C70 C45 C37 C49 C45 dbm dbm dbm dbm dbc harmonic emissions 2nd harmonic 3rd harmonic conducted measurement delivered to a 50 load, resolution bandwidth = 1mhz, video bandwidth = 1mhz. C50 C45 dbm dbm radio transmitter characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. symbol parameter conditions (note 7) min typ max units v il low level input voltage l C0.3 0.6 v v ih high level input voltage (note 8) l vsupply C 0.3 vsupply + 0.3 v v ol low level output voltage type 1, i ol(max) = 1.2ma l 0.4 v v oh high level output voltage type 1, i oh(max) = C0.8ma l vsupply C 0.3 vsupply + 0.3 v v ol low level output voltage type 2, low drive, i ol(max) = 2.2ma l 0.4 v v oh high level output voltage type 2, low drive, i oh(max) = C1.6ma l vsupply C 0.3 vsupply + 0.3 v v ol low level output voltage type 2, high drive, i ol(max) = 4.5ma l 0.4 v v oh high level output voltage type 2, high drive, i oh(max) = C3.2ma l vsupply C 0.3 vsupply + 0.3 v input leakage current input driven to vsupply or gnd 50 na pull-up/pull-down resistance 50 k digital i/o characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. parameter conditions min typ max units offset temperature offset error at 25c 0.25 c slope error 0.033 c/c temperature sensor characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 8 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr system characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. symbol parameter conditions (note 7) min typ max units permitted rx baud rate error both application programming interface (api) and command line interface (cli) uarts l C2 2 % generated tx baud rate error both api and cli uarts l C1 1 % t rx_rts to rx_cts assertion of uart_rx_rtsn to assertion of uart_rx_ctsn, or negation of uart_rx_ rtsn to negation of uart_rx_ctsn l 0 2 ms t rx_cts to rx assertion of uart_rx_ctsn to start of byte l 0 20 ms t eop to rx_rts end of packet (end of the last stop bit) to negation of uart_rx_rtsn l 0 22 ms t beg_tx_rts to tx_cts assertion of uart_tx_rtsn to assertion of uart_tx_ctsn l 0 22 ms t end_tx_cts to tx_rts negation of uart_tx_ctsn to negation of uart_tx_rtsn 2 bit period t tx_cts to tx assertion of uart_tx_ctsn to start of byte l 0 2 bit period t eop to tx_rts end of packet (end of the last stop bit) to negation of uart_tx_rtsn l 0 1 bit period t rx_interbyte receive inter-byte delay l 100 ms t rx_interpacket receive inter-packet delay l 20 ms t tx_interpacket transmit inter-packet delay l 1 bit period t tx to tx_cts start of byte to negation of uart_tx_ctsn l 0 s uart ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 12) symbol parameter conditions (note 7) min typ max units doze to active state transmit 5 s doze to radio tx or rx 1.2 ms q cca charge to sample rf channel rssi charge consumed starting from doze state and completing an rssi measurement 4 c q max largest atomic charge operation flash erase, 21ms max duration l 200 c resetn pulse width l 125 s total capacitance note 12 l 6 f total inductance note 12 l 3 h number of nodes in network (note 12) without external sram with external sram l 32 100 motes motes network upstream throughput (note 12) without external sram with external sram l 24 36 pkts/s pkts/s downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 9 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr figure 1. api uart timing symbol parameter conditions (note 7) min typ max units t strobe timen signal strobe width l 125 s t response delay from rising edge of timen to the start of time packet on api uart l 0 100 ms t time_hold delay from end of time packet on api uart to falling edge of subsequent timen l 0 ns timestamp resolution (note 9) l 1 s network-wide time accuracy (note 10) l 5 s time ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 12) figure 2. timestamp timing uart ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 12) 59012ipr f01 uart_tx_rtsn uart_tx_ctsn uart_tx byte 0 byte 1 t tx_rts to tx_cts t end_tx_cts to tx_rts t tx_cts to tx t tx to tx_cts t eop to tx_rts t end_tx_ r ts to tx_cts uart_rx_rtsn uart_rx_ctsn t rx_rts to rx_cts uart_rx t eop to rx_rts t rx_interpacket t rx_rts to rx_cts t rx_cts to rx t rx_interbyte byte 0 byte 1 t tx_interpacket 59012ipr f02 timen uart_tx t strobe t time_hold t response time indication payload downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 10 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr flash spi slave ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 12) symbol parameter conditions (note 7) min typ max units t fp_en_to_reset setup from assertion of flash_p_enn to assertion of resetn l 0 ns t fp_enter delay from the assertion resetn to the first falling edge of ipcs_ssn l 125 s t fp_exit delay from the completion of the last flash spi slave transaction to the negation of resetn and flash_p_enn l 10 s t sss ipcs_ssn setup to the leading edge of ipcs_sck l 15 ns t ssh ipcs_ssn hold from trailing edge of ipcs_sck l 15 ns t ck ipcs_sck period l 300 ns t dis ipcs_mosi data setup l 15 ns t dih ipcs_mosi data hold l 5 ns t dov ipcs_miso data valid l 3 ns t off ipcs_miso data three-state l 0 30 ns symbol parameter conditions (note 7) min typ max units t write time to write a 32-bit word (note 11) l 21 ms t page_erase time to erase a 2k byte page (note 11) l 21 ms t mass_erase time to erase 256k byte flash bank (note 11) l 21 ms data retention 25c 85c 105c 100 20 8 years y ears years flash ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 12) symbol parameter conditions (note 7) min typ max units t radio_off delay from rising edge of radio_inhibit to radio disabled l 20 ms t radio_inhibit_strobe maximum radio_inhibit strobe width l 2 s radio_inhibit ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 12) figure 3. radio_inhibit timing 59012ipr f03 radio_inhibit radio state t radio_off t radio_inhibit_strobe active/off active/off off downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 11 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr figure 4. flash programming interface timing 59012ipr f04 ipcs_sck ipcs_mosi ipcs_ssn resetn flash_p_enn t fp_en_to_reset t fp_enter t sss t dis t dih t ck t ssh t fp_exit flash spi slave ac characteristics external bus ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 12) symbol parameter conditions min typ max units t lepw eb_io_le0, eb_io_le1, eb_io_le2 pulse width l 100 ns t ah eb_data_[7:0] address hold from the rising edge of eb_io_le0, eb_io_le1, and eb_io_le2 eb_data_[7:0] during address phase l 90 ns t av_to_dl eb_addr_[1:0] address valid until eb_data_[7:0] data latched l 90 ns t csn_to_oen eb_cs0n asserted until eb_oen asserted l 150 ns t csn eb_cs0n asserted l 100 ns t su_to_csn eb_addr_[1:0], eb_io_wen setup to eb_csn asserted l 50 ns t h_from_csn eb_addr_[1:0], eb_io_wen hold from eb_csn negated l 50 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 12) downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 12 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr external bus ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 12) figure 5. external bus read timing figure 6. external bus write timing 59012ipr f06 eb_data_[7:0] a[25:18] a[17:10] a[9:2] d[31:24] d[23:16] d[7:0] d[15:8] x x eb_io_le2 eb_io_le1 eb_io_le0 t lepw t lepw t lepw t h_from_csn t su_to_csn t csn t csn_off eb_addr_[1:0] t ah t ah t ah eb_io_wen eb_io_cs0n 11 xx 10 01 00 00 59012ipr f05 eb_data_[7:0] a[25:18] a[17:10] a[9:2] d[31:24] d[23:16] d[7:0] d[15:8] x x eb_io_le2 eb_io_le1 eb_io_le0 t lepw t lepw t lepw t csn_off t av_to_dl t csn_to_oen eb_addr_[1:0] t ah t ah t ah eb_io_cs0n eb_io_oen 11 xx 10 01 00 downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 13 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: esd (electrostatic discharge) sensitive device. esd protection devices are used extensively internal to eterna. however, high electrostatic discharge can damage or degrade the device. use proper esd handling precautions. note 3: extended storage at high temperature is discouraged, as this negatively affects the data retention of eternas calibration data. see flash data retention section for details. note 4: actual rf range is subject to a number of installation-specific variables including, but not restricted to ambient temperature, relative humidity, presence of active interference sources, line-of-sight obstacles, and near-presence of objects (for example, trees, walls, signage, and so on) that may induce multipath fading. as a result, range varies. note 5: as specified by ieee std. 802.15.4-2006: wireless medium access control (mac) and physical layer (phy) specifications for low- rate wireless personal area networks (lr-wpans) http://standards.ieee. org/findstds/standard/802.15.4-2011.html . note 6: ieee std. 802.15.4-2006 requires transmitters to maintain a frequency tolerance of better than 40ppm.note 7: per pin i/o types are provided in the pin functions section. note 8: v ih maximum voltage input must respect the vsupply maximum voltage specification.note 9: see the smartmesh ip manager api guide for the time indication notification definition. note 10: network time accuracy is a statistical measure and varies over the temperature range, reporting rate and the location of the device relative to the manager in the network. see typical performance characteristics section for a more detailed description. note 11: code execution from flash banks being written or erased is suspended until completion of the flash operation.note 12: guaranteed by design. not production tested. external bus ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 12) downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 14 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr typical performance characteristics in mesh networks data can propagate from the manager to the nodes, downstream, or from the motes to the man - ager, upstream, via a sequence of transmissions from one device to the next. as shown in figure 8, data originating from mote p1 may propagate to the manager directly or through p2 . as mote p1 may directly communicate with the manager, mote p1 is referred to as a 1- hop mote. data originating from mote d1 , must propagate through at least one other mote, p2 or p1 , and as a result is referred to as a 2- hop mote. the fewest number of hops from a mote to the manager determines the hop depth.as described in the application time synchronization section, eterna provides two mechanisms for applications to maintain a time base across a network. the synchro - nization performance plots that follow were generated using the more precise timen input. publishing rate is the rate a mote application sends upstream data. syn - chronization improves as the publishing rate increases. baseline synchronization performance is provided for a network operating with a publishing rate of zero. actual performance for applications in network will improve as publishing rates increase. all synchronization testing was performed with the 1- hop mote inside a temperature chamber. timing errors due to temperature changes and temperature differences both between the manager and this mote and between this mote and its descendents therefore propagated down through the network. the synchronization of the 3- hop and 5- hop motes to the manager was thus affected by the temperature ramps even though they were at room temperature. for 2c/ minute testing the temperature chamber was cycled between C 40 c and 85 c at this rate for 24 hours. for 8c /minute testing, the temperature chamber was rapidly cycled between 85 c and 45 c for eight hours, followed by rapid cycling between C5c and 45 c for eight hours, and lastly, rapid cycling between C 40 c and 15 c for eight hours. figure 8. example network graph figure 7a. supply current vs packet rate figure 7b. packet latency vs reporting interval packet rate (packets/s) 0 0 supply current (ma) 0.8 1.0 1.2 2.0 59012ipr f07a 0.60.4 0.2 1.6 1.81.4 30 5 10 15 20 25 reporting interval (s) 0 0 median latency (s) 1.0 1.5 2.5 59012ipr f07b 0.5 2.0 30 5 10 15 20 25 5 hops4 hops 3 hops 2 hops 1 hop manager 1 hop2 hop 3 hop 5800ipm f08 p1 p2 p3 d1 d2 downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 15 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr typical performance characteristics timen synchronization error 0 packet/s publishing rate, 1 hop, room temperature timen synchronization error 0 packet/s publishing rate, 1 hop, 2c/min. timen synchronization error 0 packet/s publishing rate, 1 hop, 8c/min. timen synchronization error 0 packet/s publishing rate, 3 hops, room temperature timen synchronization error 0 packet/s publishing rate, 3 hops, 2c/min. timen synchronization error 0 packet/s publishing rate, 3 hops, 8c/min. timen synchronization error 0 packet/s publishing rate, 5 hops, room temperature timen synchronization error 0 packet/s publishing rate, 5 hops, 2c/min. timen synchronization error 0 packet/s publishing rate, 5 hops, 8c/min. synchronization error (s) C40 normalized frequency of occurance (%) 30 40 C10 40 59012ipr g01 20 10 0 C30 C20 0 10 20 30 50 60 = 0.0 = 0.9 n = 89700 synchronization error (s) C40 normalized frequency of occurance (%) 15 20 C10 40 59012ipr g02 10 5 0 C30 C20 0 10 20 30 25 30 = C0.2 = 1.7 n = 89699 synchronization error (s) C40 normalized frequency of occurance (%) 8 10 C10 40 59012ipr g03 6 42 0 C30 C20 0 10 20 30 12 14 = C0.2 = 3.6 n = 89698 synchronization error (s) C40 normalized frequency of occurance (%) 10 15 C10 40 59012ipr g04 5 0 C30 C20 0 10 20 30 20 = 1.5 = 3.3 n = 93812 synchronization error (s) C40 normalized frequency of occurance (%) 8 10 C10 40 59012ipr g05 6 42 0 C30 C20 0 10 20 30 12 14 = 0.9 = 3.9 n = 93846 synchronization error (s) C40 normalized frequency of occurance (%) 4 5 C10 40 59012ipr g06 3 21 0 C30 C20 0 10 20 30 6 7 = 1.0 = 7.7 n = 93845 synchronization error (s) C40 normalized frequency of occurance (%) 8 C10 40 59012ipr g07 6 42 0 C30 C20 0 10 20 30 10 12 = 3.6 = 5.0 n = 88144 synchronization error (s) C40 normalized frequency of occurance (%) 8 C10 40 59012ipr g08 6 42 0 C30 C20 0 10 20 30 10 1412 = 1.1 = 3.8 n = 88179 synchronization error (s) C40 normalized frequency of occurance (%) 4 C10 40 59012ipr g09 3 21 0 C30 C20 0 10 20 30 5 76 = 1.0 = 7.4 n = 88178 downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 16 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr typical performance characteristics synchronization error (s) C40 normalized frequency of occurance (%) 40 C10 40 59012ipr g10 30 2010 0 C30 C20 0 10 20 30 50 60 = 0.0 = 1.2 n = 22753 synchronization error (s) C40 normalized frequency of occurance (%) 40 C10 40 59012ipr g11 30 2010 00 C30 C20 0 10 20 30 50 60 = C0.2 = 1.2 n = 17008 synchronization error (s) C40 normalized frequency of occurance (%) 40 C10 40 59012ipr g12 30 2010 0 C30 C20 0 10 20 30 50 = C0.2 = 1.2 n = 17007 synchronization error (s) C40 normalized frequency of occurance (%) 20 25 C10 40 59012ipr g13 15 10 5 0 C30 C20 0 10 20 30 30 35 = 0.5 = 1.9 n = 85860 synchronization error (s) C40 normalized frequency of occurance (%) 30 35 C10 40 59012ipr g13 10 5 2520 15 0 C30 C20 0 10 20 30 40 45 = 0.1 = 1.5 n = 85858 synchronization error (s) C40 normalized frequency of occurance (%) 35 C10 40 59012ipr g15 15 10 5 3025 20 0 C30 C20 0 10 20 30 = 0.1 = 1.5 n = 85855 synchronization error (s) C40 normalized frequency of occurance (%) 60 C10 40 59012ipr g16 20 10 5040 30 0 C30 C20 0 10 20 30 = 0.2 = 1.4 n = 33932 synchronization error (s) C40 normalized frequency of occurance (%) 60 C10 40 59012ipr g17 20 10 5040 30 0 C30 C20 0 10 20 30 = 0.0 = 1.3 n = 33930 synchronization error (s) C40 normalized frequency of occurance (%) C10 40 59012ipr g18 20 10 5040 30 0 C30 C20 0 10 20 30 = C1.0 = 1.3 n = 33929 timen synchronization error 1 packet/s publishing rate, 1 hop, room temperature timen synchronization error 1 packet/s publishing rate, 1 hop, 2c/min. timen synchronization error 1 packet/s publishing rate, 1 hop, 8c/min. timen synchronization error 1 packet/s publishing rate, 3 hops, room temperature timen synchronization error 1 packet/s publishing rate, 3 hops, 2c/min. timen synchronization error 1 packet/s publishing rate, 3 hops, 8c/min. timen synchronization error 1 packet/s publishing rate, 5 hops, room temperature timen synchronization error 1 packet/s publishing rate, 5 hops, 2c/min. timen synchronization error 1 packet/s publishing rate, 5 hops, 8c/min. downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 17 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr typical performance characteristics as described in the smartmesh network overview sec - tion, devices in network spend the vast majority of their time inactive in their lowest power state (doze). on a synchronous schedule a mote will wake to communicate with another mote. regularly occurring sequences which wake, perform a significant function and return to sleep are considered atomic. these operations are considered atomic as the sequence of events can not be separated into smaller events while performing a useful function. for example, transmission of a packet over the radio is an atomic operation. atomic operations may be characterized in either charge or energy. in a time slot where a mote successfully sends a packet, an atomic transmit includes setup prior to sending the message, sending the message, receiving the acknowledgment and the post processing needed as a result of the message being sent. similarly in a time slot when a mote successfully receives a packet, an atomic receive includes setup prior to listening, listen - ing until the start of the packet transition, receiving the packet, sending the acknowledge and the post processing required due to the arrival of the packet. t o ensure reliability each mote in the network is provided multiple time slots for each packet it nominally will send and for ward. the time slots are assigned to communicate upstream with at least two different motes. when combined with frequency hopping this provides temporal, spatial and spectral redundancy. given this approach a mote will often listen for a message that it will never receive, since the time slot is not being used by the transmitting mote. it has already successfully transmitted the packet. since typically three timeslots are scheduled for every one packet to be sent or forwarded, motes will perform more of these atomic idle listens than atomic transmit or atomic receive sequences. examples of transmit, receive and idle listen atomic operations are shown below. downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 18 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr typical performance characteristics figure 9. atomic operation?maximum length transmit with acknowledge, 7.25ms time slot (54.5c total charge at 3.6v) atomic operation?maximum length receive with acknowledge, 7.25ms time slot (32.6c total charge at 3.6v) atomic operation?idle listen, 7.25ms time slot (6.4c total charge at 3.6v) downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 19 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr pin functions no power supply type i/o pull description 1 gnd power - - ground connection 11 gnd power - - ground connection 20 gnd power - - ground connection 30 gnd power - - ground connection 34 gnd power - - ground connection 37 gnd power - - ground connection 42 gnd power - - ground connection 56 gnd power - - ground connection 66 gnd power - - ground connection 55 vsupply power - - power supply input to eterna the following table organizes the pins by functional groups. for those i/o with multiple functions the alternate functions are shown on the second and third line in their respective row. the no column provides the pin number. the second column lists the function. the type column lists the i/o type. the i/o column lists the direction of the signal relative to eterna. the pull column shows which signals have a fixed passive pull-up or pull-down. the description column provides a brief signal description. no radio type i/o pull description 64 radio_inhibit 1 (note 13) radio inhibit 4 gpio17 1 i/o - general purpose digital i/o 5 gpio18 1 i/o - general purpose digital i/o 6 gpio19 1 i/o - general purpose digital i/o - antenna n/a n/a - chip antenna (ltp5901) or mmcx connector (lpt5902) no analog type i/o pull description 7 ai_2 analog i - analog input 2 8 ai_1 analog i - analog input 1 9 ai_3 analog i - analog input 3 10 ai_0 analog i - analog input 0 no reset type i/o pull description 15 resetn 1 i up reset input, active low no jtag type i/o pull description 16 tdi 1 i up jtag test data in 17 tdo 1 o - jtag test data out 18 tms 1 i up jtag test mode select 19 tck 1 i down jtag test clock pin functions shown in italics are currently not supported in software. downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 20 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr pin functions no special purpose type i/o pull description 63 timen 1 (note 13) i - time capture request, active low no cli and external memory type i/o pull description 25 eb_data_7 1 i/o - external bus data bit 7 26 eb_data_6 1 i/o - external bus data bit 6 27 eb_data_4 1 i/o - external bus data bit 4 28 eb_data_0 1 i/o - external bus data bit 0 31 uartc0_tx eb_io_le0 2 o o - cli uar t 0 t ransmit external bus i/o latch enable 0 for external address bits a[25:18] 32 uartc0_rx eb_data_1 1 i i/o - cli uart 0 receive external bus data bit 1 38 eb_io_le2 1 o - external bus i/o latch enable 2 for external address bits a[9:2] 40 eb_addr_1 2 o - external bus address bit 1 41 eb_addr_0 2 o - external bus address bit 0 43 eb_data_3 1 i/o - external bus data bit 3 44 eb_data_2 1 i/o - external bus data bit 2 45 eb_data_5 1 i/o - external bus data bit 5 46 eb_io_cs0n 2 o - external bus chip select 0 47 uartc1_tx 2 o - cli uart 1 transmit 48 uartc1_rx 1 i - cli uart 1 receive 49 eb_io_wen 2 o - external bus write enable strobe 50 eb_io_oen 2 o - external bus output enable strobe no ipcs spi/flash programming (note 14) type i/o pull description 33 ipcs_miso 2 o - spi flash emulation (miso) master in slave out port 35 ipcs_mosi 1 i - spi flash emulation (mosi) master out slave in port 36 ipcs_sck 1 i - spi flash emulation (sck) serial clock port 39 ipcs_ssn 1 i - spi flash emulation slave select, active low 51 flash_p_enn eb_io_le1 1 i o up up flash program enable, active low external bus i/o latch enable 1 no api uart type i/o pull description 57 uart_rx_rtsn 1 (note 13) i - uart receive (rts) request to send, active low 58 uart_rx_ctsn 1 o - uart receive (cts) clear to send, active low 59 uart_rx 1 (note 13) i - uart receive 60 uart_tx_rtsn 1 o - uart transmit (rts) request to send, active low 61 uart_tx_ctsn 1 (note 13) i - uart transmit (cts) clear to send, active low 62 uart_tx 2 o - uart transmit note 13: these inputs are always enabled and must be driven or pulled to a valid state to avoid leakage. note 14: embedded programming over the ipcs spi bus is only available when resetn is asserted. pin functions shown in italics are currently not supported in software. downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 21 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr pin functions vsupply: system and i/o power supply. provides power to the module. the digital-interface i/o voltages are also set by this voltage. antenna: multiplexed receiver input and transmitter output pin. the impedance presented to the mmcx con - nector should be 50 , single-ended with respect to ground. resetn : the asynchronous reset signal is internally pulled up. resetting eterna will result in the arm cortex- m3 rebooting and loss of network connectivity. use of this signal for resetting eterna is not recommended, except during power-on and in-circuit programming. radio_inhibit: the radio inhibit function is currently not supported by software. radio_inhibit provides a mechanism for an external device to temporarily disable radio operation. failure to observe the timing requirements defined in the radio_inhibit ac characteristics section, may result in unreliable netowrk operation. in designs where the radio_inhibit function is not needed the input must either be tied, pulled or actively driven low to avoid excess leakage. tms, tck, tdi, tdo : jtag port supporting software debug and boundary scan. sleepn: the sleepn function is not currently supported in software. the sleepn input must either be tied, pulled or actively driven high to avoid excess leakage. uart_rx, uart_rx_rtsn, uart_rx_ctsn, uart_tx , uart_tx_rtsn, uart_tx_ctsn : the api uart interface includes bi-directional wake up and flow control. unused input signals must be driven or pulled to their ina ctive state. timen : strobing the timen input is the most accurate meth - od to acquire the network time maintained by eterna. eterna latches the network timestamp with sub-microsecond resolution on the rising edge of the timen signal and produces a packet on the api serial port containing the timing information. uartc0 _rx, uart c0 _tx, uart c1 _rx, uart c1_tx: the cli uart provides a mechanism for monitoring, configuration and control of eterna during operation. on the l tp5901/2- ipr cli uart 0 is used when eterna is not configured to support external ram and cli uart 1 is used when eterna is configured to support external ram. for a complete description of the supported commands see the smartmesh ip manager cli guide . eb_data _0 through eb_data_7, eb_addr_0, eb_ addr_1, eb_io_le1 through eb_io_le2, eb_io_cs0n, eb_io_wen, eb_io_enn: the external bus provides a multiplexed address data bus enabling the cortex- m3 direct access of external byte wide ram. the additional ram is used by network management software enabling the support of a larger network of motes with higher packet throughput. to support the addressing needed, each latch signal, eb_io_le0, eb_io_le1 , and eb_io_le2 will strobe to latch 8- bits of address from the eb_data[7:0] bus. eb_io_le0, eb_io_le1 , and eb_io_le2 correspond to addres bits [25:18], [17:10] and [9:2] respectively. eb_addr _0 and eb_addr _1 correspond to the lower two bits of address. for systems with 256k bytes or less eb_io_le 2 can be ignored. eb_io_c s0 n, eb_io_wen and eb_io_oen provide chip select, write enable and output enable control of the external ram. flash_p_enn, ipcs_ssn, ipcs_sck, ipcs_miso , ipcs_ssn: the in-circuit programming control system (ipcs) bus enables in-circuit programming of eterna s flash memory. ipcs_sck is a clock and should be terminated appropriately for the driving source to prevent overshoot and ringing. downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 22 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr operation the l tp5901/ltp5902 is the world s most energy-efficient ieee 802.15.4 compliant platform, enabling battery and energy harvested applications. with a powerful 32- bit arm cortex-m3 , best-in-class radio, flash, ram and purpose- built peripherals, eterna provides a flexible, scalable and robust networking solution for applications demanding minimal energy consumption and data reliability in even the most challenging rf environments. shown in figure 10, eterna integrates purpose-built pe - ripherals that excel in both low operating-energy c onsump - tion and the ability to rapidly and precisely cycle between operating and low power states. items in the gray shaded region labeled analog core correspond to the analog/rf components. figure 10. eterna block diagram 4-bit dac vga bpf ppf agc lpf adc dac 10-bit adc pll rssi lna pa 20mhz 32khz 32khz, 20mhz ptat 59012ipr f10 bat load limiter voltage reference analog core digital core core regulator clock regulator analog regulator pa dc/dc converter primary dc/dc converter relaxation oscillator por timers sched sram 72kb flash 512kb flash controller code aes auto mac 802.15.4 mod 802.15.4 framing dma ipcs spi slave cli uart (2 pin) api uart (6 pin) adc ctrl 802.15.4 demod system pmu/ clock control downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 23 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr operation power supply eterna is powered from a single pin, vsupply, which powers the i/o cells and is also used to generate internal supplies. eterna s two on-chip dc/dc converters minimize eterna s energy consumption while the device is awake. to conserve power the dc/dc converters are disabled when the device is in low power state. eterna s integrated power supply conditioning architecture, including the two inte - grated dc/dc converters and three integrated low dropout regulators, provides excellent rejection of supply noise. eterna s operating supply voltage range is high enough to support direct connection to lithium-thionyl chloride, li-socl2 , sources and wide enough to support battery operation over a broad temperature range. supply monitoring and reset eterna integrates a power-on reset (por) circuit. as the resetn input pin is nominally configured with an internal pull-up resistor, no connection is required. for a graceful shutdown, the software and the networking layers should be cleanly halted via api commands prior to assertion of the resetn pin. see the smartmesh ip manager api guide for details on the disconnect and reset commands. eterna includes a soft brown-out monitor that fully protects the flash from corruption in the event that power is removed while writing to flash. integrated flash supervisory func - tionality, in conjunction with a fault tolerant file system, yields a robust non-volatile storage solution. p recision timing a major feature of eterna over competing 802.15.4 prod - uct offerings is its low power dedicated timing hardware and timing algorithms. this functionality provides timing precision two to three orders of magnitude better than any other low power solution available at the time of publication. improved timing accuracy allows motes to minimize the amount of radio listening time required to ensure packet reception thereby lowering even further the power consumed by smartmesh networks. eterna s patented timing hardware and timing algorithms provide superior performance over rapid temperature changes, further differentiating eterna s reliability when compared with other wireless products. in addition, precise timing enables networks to reduce spectral dead time, increasing total network throughput. application time synchronization in addition to coordinating time slots across the network, which is transparent to the user, eterna s timing manage - ment is used to support two mechanisms to share network time. having an accurate, shared, network-wide time base enables events to be accurately time stamped or tasks to be performed in a synchronized fashion across a network. eterna will send a time packet through its serial inter face when one of the following occurs:? eterna receives an api request to read time ? the timen signal is asserted the use of timen has the advantage of being more accurate. the value of the timestamp is captured in hardware relative to the rising edge of timen. if an api request is used, due to packet processing, the value of the timestamp may be captured several milliseconds after receipt of the packet due to packet processing. see section timen ac characteristics, for the time function s definition and specifications. time references eterna includes three clock sources : an internal relaxation oscillator, a low power oscillator designed for a 32.768khz crystal, and the radio reference oscillator designed for a 20mhz crystal. relaxation oscillator the relaxation oscillator is the primary clock source for eterna, providing the clock for the cpu, memory subsys - tems, and all peripherals. the internal relaxation oscillator is dynamically calibrated to 7.3728mhz . the internal re - laxation oscillator typically starts up in a few s, providing an expedient, low energy method for duty cycling between active and low power states. quick start-up from the doze state, defined in the state diagram section, allows eterna to wake up and receive data over the uart and spi interfaces by simply detecting activity on the appropriate signals. downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 24 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr operation 32.768khz crystalonce eterna is powered up and the 32.768khz crystal source has begun oscillating, the 32.768khz crystal re - mains operational while in the active state, and is used as the timing basis when in doze state. see the state diagram section, for a description of eternas operational states. 20mhz crystal the 20mhz crystal source provides a frequency reference for the radio, and is automatically enabled and disabled by eterna as needed. radio eterna includes the lowest power commercially available 2.4ghz ieee 802.15.4e radio by a substantial margin. (please refer to section radio specifications, for power consumption numbers). eterna s integrated power ampli - fier is calibrated and temperature-compensated to con - sistently provide power at a limit suitable for worldwide radio certifications. additionally, eterna uniquely includes a hardware-based autonomous mac that handles precise sequencing of peripherals, including the transmitter, the receiver, and advanced encryption standard (aes) periph - erals. the hardware-based autonomous media access controller (mac) minimizes cpu activity, thereby further decreasing power consumption. uarts the principal network interface is through the applica - tion programming interface (api) uart. a command-line interface (cli) is also provided for support of test and debug functions. both uar ts sense activity continuously, consuming virtually no power until data is transferred over the port and then automatically returning to their lowest power state after the conclusion of a transfer. the defini - tion for packet encoding on the api uart interface can be found in the smartmesh ip manager api guide and the cli command definitions can be found in the smartmesh ip manager cli guide . api uart protocol the api uart protocol was created with the goal of sup - porting a wide range of companion multipoint control units (mcus) while reducing power consumption of the system. the receive half of the api uart protocol includes two ad - ditional signals in addition to uart_rx: uart_rx_rtsn and uart_rx_ctsn . the transmit half of the api uart protocol includes two additional signals in addition to uart_tx: uart_tx_rtsn and uart_tx_ctsn . the api uart protocol is referred to as mode 4. in the figures accompanying the protocol descriptions, signals driven by the companion processor are drawn in black and signals driven by eterna are drawn in blue. uart mode 4 uart mode 4 incorporates level-sensitive flow control on the tx channel and requires no flow control on the rx channel, supporting 115200 baud. the use of level- sensitive flow control signals enables higher data rates with the option of using a reduced set of the flow control signals; however, mode 4 has specific limitations. first, the use of the rx flow control signals ( uart_rx_rtsn and uart_rx_ctsn ) for mode 4 are optional provided the use is limited to the industrial temperature range (C40c to 85c); otherwise, the flow control is mandatory. if rx flow control signals are not used, uart_rx_rtsn should be tied to vsupply (inactive) and uart_rx_ctsn should be left unconnected. second, unless the com - panion processor is always ready to receive a packet, the companion processor must negate uart_tx_ctsn prior to the end of the current packet. failure to negate uart_tx_ctsn prior to the end of a packet may result in back to back packets. third, the companion processor must wait at least t rx_interpacket between transmitting packets on uart_rx . see the uart ac characteristics section for complete timing specifications. packets are hdlc encoded with one stop bit and no parity bit. the flow control signals for the tx channel are shown in figure 11. transfers are initiated by eterna asserting uart_tx_rtsn . downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 25 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr figure 11. uart mode 4 transmit flow control operation the uart_tx_ctsn signal may be actively driven by the companion processor when ready to receive a packet or uart_tx_ctsn may be tied low if the companion pro - cessor is always ready to receive a packet. after detecting a logic 0 on uart_tx_ctsn eterna sends the entire packet. following the transmission of the final byte in the packet eterna negates uart_tx_rtsn and waits for t tx_interpacket , defined in the uart ac characteristics section, before asserting uart_tx_rtsn again. for details on the timing of the uart protocol, see the uart ac characteristics section. to remain inactive during the majority of the radio activity. the autonomous mac, provides software-independent timing control of the radio and radio-related functions, resulting in superior reliability and exceptionally low power. security network security is an often overlooked component of a complete network solution. proper implementation of se - curity protocols is significant in terms of both engineering effort and market value in an oem product. eterna system solutions provide a fips-197 validated encryption scheme that includes authentication and encryption at the mac and network layers with separate keys for each mote. this not only yields end-to-end security, but if a mote is somehow compromised, communication from other motes is still secure. a mechanism for secure key exchange al - lows keys to be kept fresh. to prevent physical attacks, eterna includes hardware support for electronically locking devices, thereby preventing access to eterna s flash and ram memory and thus the keys and code stored therein. temperature sensor eterna includes a calibrated temperature sensor on chip. the temperature readings are available locally through eterna s serial api, in addition to being available via the network manager. the performance characteristics of the temperature sensor can be found in the temperature sensor characteristics section. radio inhibit the radio_inhibit input enables an external control - ler to temporarily disable the radio software drivers (for example, to take a sensor reading that is susceptible to radio interference). when radio_inhibit is asserted the software radio drivers will disallow radio operations including clear channel assessment, packet transmits, or packet receipts. if the radio is active in the current time slot when radio_inhibit is asserted the radio will be disabled after the present operation completes. for details on the timing associated with radio_inhibit , see the radio_inhibit ac characteristics section. cli uart the command line interface (cli) uart port is a two wire protocol (tx and rx) that operates at a fixed 9600 baud rate with one stop bit and no parity. the cli uart interface is intended to support command line instructions and response activity. autonomous mac eterna was designed as a system solution to provide a reliable, ultralow power, and secure network. a reliable network capable of dynamically optimizing operation over changing environments requires solutions that are far too complex to completely support through hardware acceleration alone. as described in the precision timing section, proper time management is essential for optimizing a solution that is both low power and reliable. to address these requirements eterna includes the autonomous mac, which incorporates a coprocessor for controlling all of the time-critical radio operations. the autonomous mac provides two benefits: first, preventing variable software latency from affecting network timing and second, greatly reducing system power consumption by allowing the cpu 59012ipr f11 uart_tx byte 0 byte 1 uart_tx_ctsn uart_tx_rtsn downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 26 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr software installation devices are supplied with the flash erased, requiring pro - gramming as part of the oems manufacturing procedure. the us department of commerce places restrictions on export of systems and software supporting encryption. all of linear/dust product software produced to date contains encryption and is subject to export regulations and may be provided only via mylinear , https://www. linear.com/mylinear . customers purchasing smartmesh products will receive a certificate containing a registration key and registration instructions with their order. after registering with the key, customers will be able to download smartmesh software images from mylinear . once registered, customers will receive automated e-mail notifications as software updates are made avaialbe. linear technology offers the dc9010 , in circuit program - mer for the eterna based products. while the dc9010 , is provided as a finished product, the design documents are provided as a reference for customers. once software has been loaded, devices can be configured via either the cli or api ports. configuration commands and settings are defined in smartmesh ip manager api guide and smartmesh ip manager cli guide . flash data retention eterna contains internal flash (non-volatile memory) to store calibration results, unique id, configuration settings and software images. flash retention is specified over the operating temperature range. see electrical characteristics and absolute maximum ratings sections. non destructive storage above the operating temperature range of C40c to 85c is possible ; although, this may result in a degradation of retention characteristics.the degradation in flash retention for temperatures >85c can be approximated by calculating the dimensionless acceleration factor using the following equation. af = e ea k ?? ? ?? ? ? 1 t use + 273 ? 1 t stress + 273 ?? ? ?? ? ?? ? ? ?? ? ? where:af = acceleration factor ea = activation energy = 0.6ev k = 8.625 ? 10 C5 ev/ k t use = is the specified temperature retention in c t stress = actual storage temperature in c example: calculate the effect on retention when storing at a temperature of 105c.t stress = 105c t use = 85c af = 2.8so the overall retention of the flash would be degraded by a factor of 2.8, reducing data retention from 20 years at 85c to 7.1 years at 105c. networking the l tp5901-ipr/ltp5902 -ipr network manager pro - vides the ingress/egress point for at the wired to wireless mesh network boundary , via the api uart interface. the complexity of the mesh network management is handled entirely within the embedded software, which provides dynamic network optimization, deterministic power man - agement, intelligent routing, and configurable bandwidth allocation while achieving carrier class data reliability and low power operation.dynamic network optimization dynamic network optimization allows eterna to address the changing rf requirements in harsh industrial en - vironments resulting in a network that is continuously self-monitoring and self-adjusting. the manager performs dynamic network optimization based upon periodic re ports on network health and link quality that it receives from the network motes. the manager uses this information to provide performance statistics to the application layer and proactively solve problems in the network. dynamic operation downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 27 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr network optimization not only maintains network health, but also allows eterna to deliver deterministic power management. one of the key advantages of smartmesh networking solutions is the network manager is aware of and tracking the success or failure of every packet trans - action, so not only can the network be optimized, but the solution can be rigorously tested to produce a system solution with better than 99.999% reliability . deterministic power managementdeterministic power management balances traffic in the network by diverting traffic around heavily loaded motes (for example, motes with high reporting rates). in do - ing so, it reduces power consumption for these motes and balances power consumption across the network. deterministic power management provides predictable maintenance schedules to prevent down time and lower the cost of network ownership. when combined with field devices using eterna s industry-leading low power radio technology, deterministic power management enables over a decade of battery life for network motes. intelligent routing intelligent routing provides each packet with an optimal path through the network. the shortest distance between two points is a straight line, but in rf the quickest path is not always the one with the fewest hops. intelligent routing finds optimal paths by considering the link quality (one path may lose more packets than another) and the retry schedule, in addition to the number of hops. the result is reduced network power consumption, elimination of in-network collisions, and unmatched network scalability and reliability. configurable bandwidth allocation smartmesh networks provide configurations that enable users to make bandwidth and latency versus power trade- offs both network-wide and on a per device basis. this flexibly enables solutions that tailored to the application requirements, such as request/response, fast file trans - fer, and alerting. relevant configuration parameters are described in the smartmesh ip users guide . the design trade-offs between network performance and current consumption are supported via the smartmesh power and performance estimator . ip manager optionsthe ip manager can operate with or without external sram, as described in the ltp5901 and l tp5902 inte - gration guide . when used without external sram, the ip manager is limited to managing networks of 32 motes or fewer and is limited to a maximum packet throughput of 24 packets per second. with external sram, the ip manager supports managing networks of up to 100 motes and the packet throughput of the ip manager increases from 24 packets per second to 36 packets per second. state diagram in order to provide capabilities and flexibility in addition to ultra low power, eterna operates in various states, as shown in figure 12 eterna state diagram and described in this section. state transitions shown in red are not recommended. start-up start-up occurs as a result of either crossing the power-on reset threshold or asserting resetn. after the comple - tion of power-on reset or the falling edge of an internally synchronized resetn, eterna loads its fuse table which, as described in the previous section, includes setting i/o direction. in this state, eterna checks the state of the flash_p_enn and resetn and enters the serial flash emulation mode if both signals are asserted. if the flash_p_enn pin is not asserted but resetn is asserted, eterna automatically reduces its energy consumption to a minimum until resetn is released. once resetn is de-asserted, eterna goes through a boot sequence, and then enters the active state. operation downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 28 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr figure 12. eterna state diagram serial flash emulationwhen both resetn and flash_p_enn are asserted, eterna disables normal operation and enters a mode to emulate the operation of a serial flash. in this mode, its flash can be programmed. operationonce eterna has completed start-up, eterna transitions to the operational group of states (active/cpu active, active/ cpu inactive, and doze). there, eterna cycles between the various states, automatically selecting the lowest pos - sible power state while fulfilling the demands of network operation. serial flash emulation load fuse settings resetn low and flash_p_enn high resetn high and flash_p_enn high reset deassert resetn cpu and peripherals inactive hw or pmu event boot start-up operation inactive doze deep sleep low power sleep command 59012ipr f12 assert resetn assert resetn assert resetn cpu active cpu inactive power-on reset resetn low and flash_p_enn low set resetn high and flash_p_enn high for 125s, then set resetn low vsupply > por active operation downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 29 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr doze statethe doze state consumes orders of magnitude less cur - rent than the active state and is entered when all of the peripherals and the cpu are inactive. in the doze state eterna s full state is retained, timing is maintained, and eterna is configured to detect, wake, and rapidly respond to activity on i/os (such as uart signals and the timen pin). in the doze state the 32.768khz oscillator and as - sociated timers are active. active state in the active state, eterna s relaxation oscillator is running and peripherals are enabled as needed. the arm cortex-m3 cycles between cpu-active and cpu-inactive (referred to in the arm cortex- m3 literature as sleep now mode). eterna s extensive use of dma and intelligent peripherals that independently move eterna between active state and doze state minimizes the time the cpu is active, signifi - cantly reducing eternas energy consumption. operation regulatory and standards compliance radio certification the l tp5901 and l tp5902 have been certified under a single modular certification, with the module name of eterna2 . following the regulatory requirements provided in the eterna2 users guide can enable customers to ship products in the supported geographies, by simply completing an unintentional radiator scan of the finished product(s). the eterna2 users guide also provides the technical information needed to enable customers to fur - ther certify either the modules or products based upon the modules in geographies that have not or do not support modular certification. compliance to restriction of hazardous substances (rohs) restriction of hazardous substances 2(rohs 2) is a directive that places maximum concentration limits on the use of certain hazardous substances in electrical and electronic equipment. linear technology is committed to meeting the requirements of the european community directive 2011/65/eu. this product has been specifically designed to utilize rohs-compliant materials and to eliminate or reduce the use of restricted materials to comply with 2011/65/eu. applications information the rohs-compliant design features include:? rohs-compliant solder for solder joints ? rohs-compliant base metal alloys ? rohs-compliant precious metal plating ? rohs-compliant cable assemblies and connector choices? halogen-free mold compound ? rohs-compliant and 245c re-flow compatible note: customers may elect to use certain types of lead- free solder alloys in accordance with the european com - munity directive 2011/65/eu. depending on the type of solder paste chosen, a corresponding process change to optimize reflow temperatures may be required. s oldering information the l tp5901 and l tp5902 are suitable for both eutectic pbsn and rohs-6 reflow. the maximum reflow solder - ing temperature is 260c . a more detailed description of layout recommendations, assembly procedures and design considerations is included in the ltp5901 and l tp5902 hardware integration guide . downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 30 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr related documentation title location description smartmesh ip users guide http://www.linear.com/docs/41880 theory of operation for smartmesh ip networks and motes smartmesh ip manager api guide http://www.linear.com/docs/41883 definitions of the applications interface commands available over the api uart smartmesh ip manager cli guide http://www.linear.com/docs/41882 definitions of the command line interface commands available over the cli uart ltp5901 and ltp5902 hardware integration guide http://www .linear.com/docs/41877 recommended practices for designing with the ltp5901 and ltp5902 eterna2 users guide http://www.linear.com/docs/42916 the eterna2 module users guide covering certification requirements for certified geographies and support documentation enabling customer certification in additional geographies for the ltp5901 and ltp5902 smartmesh ip tools guide http://www.linear.com/docs/42453 the users guide for all ip related tools, and specifically the definition for the on-chip application protocol (oap) downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 31 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr package description please refer to http://www.linear.com/product/ltp5901-ipr#packaging for the most recent package drawings. figure 13. ltp5901 mechanical drawing r.010 0.25 typ .0391.00 typ .039 1.00 4x .035 0.90 .039 1.00 0 0.00 .08 2.00 .157 4.00 .197 5.00 .236 6.00 .344 8.74 .444 11.28 .551 14.00 .591 15.00 .630 16.00 .87 22.00 .728 18.50 .394 10.00 0 0.00 .08 2.00 .039 1.00 .039 1.00 .079 2.00 1.102 28.00 1.063 27.00 1.031 26.20 1.122 28.50 1.213 30.80 1.57 40.00 .0391.00 1.65442.00 .100 2.54 .0391.00 .945 24.00 59012ipr f12 downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 32 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr package description please refer to http://www.linear.com/product/ltp5901-ipr#packaging for the most recent package drawings. figure 14. ltp5902 mechanical drawing .0391.00 typ r.010 0.25 typ .039 1.00 .039 1.00 4x .035 0.90 0 0.00 .078 2.0 .157 4.00 .197 5.00 .236 6.00 .344 8.73 .444 11.28 .866 22.00 .394 10.00 0 0.00 .079 2.01 .039 1.00 .039 1.00 .079 2.00 1.031 26.20 1.213 30.80 1.40 35.50 1.122 28.50 1.102 28.00 1.272 32.30 1.063 27.00 .071 1.80 .728 18.50 .551 14.00 .591 15.00 .630 16.00 1.47637.50 .0391.00 .0290.73 .1002.54 .0391.00 .1774.50 .945 24.00 59012ipr f13 downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 33 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 11/15 updated ordering part number options. added total inductance, capacitance.added software installation section. 5, 27 8 26 downloaded from: http:///
ltp5901-ipr/ltp5902-ipr 34 59012iprfa for more information www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr ? linear technology corporation 2014 lt 1115 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltp5901-ipr or www.linear.com/ltp590 2-ipr power over ethernet network manager related parts typical application part number description comments ltc5800-ipr ip wireless mesh manager qfn network manager ltp5901-ipm ip wireless mesh mote pcb module with chip antenna includes modular radio certification in the united states, canada, europe, japan, south korea, taiwan, india, australia and new zealand ltp5902-ipm ip wireless mesh mote pcb module with mmcx antenna connector includes modular radio certification in the united states, canada, europe, japan, south korea, taiwan, india, australia and new zealand ltc2379-18 18-bit,1.6msps/1msps/500ksps/ 250ksps serial, low power adc 2.5v supply, differential input, 101.2db snr, 5v input range, dgc ltc3388-1/ltc3388-3 20v high efficiency nanopower step-down regulator 860na i q in sleep, 2.7v to 20v input, v out : 1.2v to 5.0v, enable and standby pins ltc3588-1 piezoelectric energy generator with integrated high efficiency buck converter v in : 2.7v to 20v; v out(min) : fixed to 1.8v, 2.5v, 3.3v, 3.6v; i q = 0.95a; 3mm 3mm dfn-10 and msop-10e packages ltc3108-1 ultralow voltage step-up converter and power manager v in : 0.02v to 1v; v out = 2.5v, 3v, 3.7v, 4.5v fixed; i q = 6a; 3mm 4mm dfn-12 and ssop-16 packages ltc3459 micropower synchronous boost converter v in : 1.5v to 5.5v; v out(max) = 10v; i q = 10a; 2mm 2mm dfn, 2mm 3mm dfn or sot-23 package ltc4265 ieee 802.3at high power pd interface controller with 2-event classification 2-event classification recognition, 100ma inrush current, single-class programming resistor, full compliance to 802.3at lt8300 100v micropower isolated flyback converter with 150v/260ma switch 6v v in 100v, no opto flyback , 5-lead tsot-23 package 59012ipr ta02 rj45 tx + 12 3 6 4 5 7 8 14 1 12 13 10 11 9 32 5 4 6 tx ? rx + rx ? coilcraft ethi - 230ld 0.1f 100v smaj58a tvs lt4265 (poe pd interface controller) lt8300 (isolated flyback converter) 3.3v rxm rxp mii smsc 8710a (10/100 phy) txm txp uart mii atmel sam4e pwm uart ltp5902-ipr timen antenna downloaded from: http:///

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